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| E n n n n n 5 VOLT BOOT BLOCK FLASH MEMORY 28F001BX (x8) High-Integration Blocked Architecture One 8 KB Boot Block w/Lock Out Two 4 KB Parameter Blocks One 112 KB Main Block Simplified Program and Erase Automated Algorithms via On-Chip Write State Machine (WSM) SRAM-Compatible Write Interface Deep Power-Down Mode 0.05 A ICC Typical 0.8 A IPP Typical 12.0 V 5% VPP n n n n High-Performance Read 120 ns, 150 ns Maximum Access Time 5.0 V 10% VCC Hardware Data Protection Feature Erase/Write Lockout during Power Transitions Advanced Packaging, JEDEC Pinouts 32-Pin PDIP 32-Lead PLCC ETOXTM II Nonvolatile Flash Technology EPROM-Compatible Process Base High-Volume Manufacturing Experience The Intel(R) 28F001BX-B and 28F001BX-T combine the cost-effectiveness of Intel standard flash memory with features that simplify write and allow block erase. These devices aid the system designer by combining the functions of several components into one, making boot block flash an innovative alternative to EPROM and EEPROM or battery-backed static RAM. Many new and existing designs can take advantage of the 28F001BX's integration of blocked architecture, automated electrical reprogramming, and standard processor interface. The 28F001BX-B and 28F001BX-T are 1,048,576 bit nonvolatile memories organized as 131,072 bytes of eight bits. They are offered in 32-pin plastic DIP and 32-lead PLCC packages. Pin assignment conform to JEDEC standards for byte-wide EPROMs. These devices use an integrated command port and state machine for simplified block erasure and byte reprogramming. The 28F001BX-T's block locations provide compatibility with microprocessors and microcontrollers that boot from high memory, such as Intel(R) MCS(R)186 family, 80286, i386TM, i486TM, i860TM and 80960CA. With exactly the same memory segmentation, the 28F001BX-B memory map is tailored for microprocessors and microcontrollers that boot from low memory, such as Intel's MCS-51, MCS-196, 80960KX and 80960SX families. All other features are identical, and unless otherwise noted, the term 28F001BX can refer to either device throughout the remainder of this document. The boot block section includes a reprogramming write lock out feature to guarantee data integrity. It is designed to contain secure code which will bring up the system minimally and download code to the other locations of the 28F001BX. Intel 28F001BX employs advanced CMOS circuitry for systems requiring highperformance access speeds, low-power consumption, and immunity to noise. Its access time provides zero wait-state performance for a wide range of microprocessors and microcontrollers. A deep power-down mode lowers power consumption to 0.25 W typical through VCC--crucial in laptop computer, hand-held instrumentation and other low-power applications. The RP# power control input also provides absolute data protection during system power-up or power loss. Manufactured on Intel(R) ETOXTM process technology base, the 28F001BX builds on years of EPROM experience to yield the highest levels of quality, reliability, and cost-effectiveness. Note: This document formerly known as 1-Mbit (128K x 8) Boot Block Flash Memory. December 1998 Order Number: 290406-009 INTEL CONFIDENTIAL (until publication date) Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. The 28F001BX-T/28F001BX-B may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from: Intel Corporation P.O. Box 5937 Denver, CO 8021-9808 or call 1-800-548-4725 or visit Intel's website at http://www.intel.com COPYRIGHT (c) INTEL CORPORATION 1997, 1998 CG-041493 *Third-party brands and names are the property of their respective owners. 2 E 28F001BX CONTENTS PAGE PAGE 7.0 ON-CHIP ERASE ALGORITHM.................... 17 8.0 BOOT BLOCK PROGRAM AND ERASE ..... 18 8.1 In-System Operation .................................. 18 8.1.1 Programming Equipment..................... 18 9.0 DESIGN CONSIDERATIONS........................ 22 9.1 Power Supply Decoupling .......................... 22 9.2 VPP Trace on Printed Circuit Boards .......... 22 9.3 VCC, VPP, RP# Transitions and the Command/Status Registers ...................... 22 9.4 Power-Up/Down Protection........................ 22 9.5 28F001BX Power Dissipation .................... 23 10.0 ELECTRICAL SPECIFICATIONS .............. 24 10.1 Absolute Maximum Ratings ..................... 24 10.2 Operating Conditions ............................... 24 10.3 Capacitance............................................ 24 10.4 DC Characteristics .................................. 25 10.5 AC Characteristics--Read-Only Operations ................................................ 29 10.6 AC Characteristics--Write/Erase/Program Operations ................................................ 31 10.6.1 PROM Programmer Specifications.... 32 10.7 Erase and Programming Performance .... 32 10.8 AC Characteristics--CE#-Controlled Write Operations ................................................ 36 10.8.1 PROM Programmer Specifications.... 37 11.0 ORDERING INFORMATION ...................... 39 12.0 ADDITIONAL INFORMATION.................... 39 1.0 APPLICATIONS.............................................. 5 2.0 PRINCIPLES OF OPERATION..................... 10 2.1 Command Register and Write Automation. 11 2.2 Data Protection.......................................... 11 3.0 BUS OPERATION ........................................ 11 3.1 Read.......................................................... 12 3.2 Output Disable........................................... 12 3.3 Standby ..................................................... 12 3.4 Deep Power-Down..................................... 13 3.5 Intelligent Identifier Operation .................... 13 3.5.1 Programming Equipment .................... 13 3.5.2 In-System Programming ..................... 13 3.6 Write .......................................................... 13 4.0 COMMAND DEFINITIONS............................ 13 4.1 Read Array Command ............................... 13 4.2 Intelligent Identifier Command for In-System Programming ............................................ 14 4.3 Read Status Register Command ............... 15 4.4 Clear Status Register Command ............... 15 4.5 Erase Setup/Erase Confirm Commands .... 15 4.6 Erase Suspend/Erase Resume Commands15 4.7 Program Setup/Program Commands ......... 17 5.0 EXTENDED ERASE/PROGRAM CYCLING . 17 6.0 ON-CHIP PROGRAMMING ALGORITHM .... 17 3 28F001BX E REVISION HISTORY Description Removed Preliminary classification. Latched address A16 in Figure 5. Updated Boot Block Program and Erase section: "If boot block program or erase is attempted while RP# is at V IH, either the Program Status or Erase Status bit will be set to `1,' reflective of the operation being attempted and indicating boot block lock." Updated Figure 11, 28F001BX Erase Suspend/Resume Flowchart. Added DC Characteristics typical current values. Combined VPP Standby current and VPP Read current into one VPP Standby current spec with two test conditions (DC Characteristics table). Added maximum program/erase times to Erase and Programming Performance table. Added Figures 13-16. Added Extended Temperature proliferations. -------------- Number -004 -005 PWD changed to RP# for JEDEC standardization compatibility. ---------- -------- Revised symbols, i.e.; CE, OE, etc. to CE#, OE#, etc. -006 -007 -008 Added specifications for -90 and -70 product versions. Added VOH CMOS Specification. Added reference to 28F001BN. Removed Extended Temperature products. Removed 70 ns and 90 ns speeds. Removed TSOP package. Updated Erase Suspend/Resume Flowchart. Updated Ordering Information table. Removed reference to 28F001BN. Changed ICCD typical and maximum current values -009 4 E 28F001BX parameter blocks, while still providing recovery code in the boot block in the unlikely event a power failure occurs during an update, or where BIOS code is corrupted. Parameter blocks also provide convenient configuration storage, backing up SRAM and battery configurations. EISA systems, for example, can store hardware configurations in a flash parameter block, reducing system SRAM. Laptop BIOS are becoming increasingly complex with the addition of power management software and extended system setup screens. BIOS code complexity increases the potential for code updates after the sale, but the compactness of laptop designs makes hardware updates very costly. Boot block flash memory provides an inexpensive update solution for laptops, while reducing laptop obsolescence. For portable PCs and hand-held equipment, the deep power-down mode dramatically lowers system power requirements during periods of slow operation or sleep modes. The 28F001BX gives the embedded system designer several desired features. The internal state machine reduces the size of external code dedicated to the erase and program algorithms, as well as freeing the microcontroller or microprocessor to respond to other system requests during program and erasure. The four blocks allow logical segmentation of the entire embedded software: the 8-Kbyte block for the boot code, the 112-Kbyte block for the main program code and the two 4-Kbyte blocks for updatable parametric data storage, diagnostic messages and data, or extensions of either the boot code or program code. The boot block is hardware protected against unauthorized write or erase of its vital code in the field. Further, the power-down mode also locks out erase or write operations, providing absolute data protection during system power-up or power loss. This hardware protection provides obvious advantages for safety related applications such as transportation, military, and medical. The 28F001BX is well suited for minimum-chip embedded applications ranging from communications to automotive. 1.0 APPLICATIONS The Intel(R) 28F001BX Flash Boot Block memory augments the nonvolatility, in-system electrical erasure and reprogrammability of Intel's flash memory by offering four separately erasable blocks and integrating a state machine to control erase and program functions. The specialized blocking architecture and automated programming of the 28F001BX provide a full-function, nonvolatile flash memory ideal for a wide range of applications, including PC boot/BIOS memory, minimum-chip embedded program memory and parametric data storage. The 28F001BX combines the safety of a hardware-protected 8-Kbyte boot block with the flexibility of three separately reprogrammable blocks (two 4-Kbyte parameter blocks and one 112-Kbyte code block) into one versatile, cost-effective flash memory. Additionally, reprogramming one block does not affect code stored in another block, ensuring data integrity. The flexibility of flash memory reduces costs throughout the life cycle of a design. During the early stages of a system's life, flash memory reduces prototype development and testing time, allowing the system designer to modify in-system software electrically versus manual removal of components. During production, flash memory provides flexible firmware for just-in-time configuration, reducing system inventory and eliminating unnecessary handling and less reliable socketed connections. Late in the life cycle, when software updates or code "bugs" are often unpredictable and costly, flash memory reduces update costs by allowing the manufacturers to send floppy updates versus a technician. Alternatively, remote updates over a communication link are possible at speeds up to 9600 baud due to flash memory's fast programming time. Reprogrammable environments, such as the personal computer, are ideal applications for the 28F001BX. The internal state machine provides SRAM-like timings for program and erasure, using the command and status registers. The blocking scheme allows BIOS update in the main and 5 28F001BX E 29040601 Figure 1. 28F001BX Block Diagram 6 E Table 1. Lead Descriptions Symbol A0-A16 DQ0-DQ7 Type INPUT Name and Function CE# INPUT RP# INPUT 28F001BX ADDRESS INPUTS for memory addresses. Addresses are internally latched during a write cycle. INPUT/ DATA INPUTS/OUTPUTS: Inputs data and commands during memory write OUTPUT cycles; outputs data during memory, status register and identifier read cycles. The data pins are active high and float to tri-state off when the chip is deselected or the outputs are disabled. Data is internally latched during a write cycle. CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense amplifiers. CE# is active low; CE# high deselects the memory device and reduces power consumption to standby levels. POWERDOWN: Puts the device in deep power-down mode. RP# is active low; RP# high gates normal operation. RP# = VHH allows programming of the boot block. RP# also locks out erase or write operations when active low, providing data protection during power transitions. RP# active resets internal automation. Exit from deep power-down sets device to read array mode. OUTPUT ENABLE: Gates the device's outputs through the data buffers during a read cycle. OE# is active low. OE# = V HH (pulsed) allows programming of the boot block. WRITE ENABLE: Controls writes to the command register and array blocks. WE# is active low. Addresses and data are latched on the rising edge of the WE# pulse. ERASE/PROGRAM POWER SUPPLY for erasing blocks of the array or programming bytes of each block. Note: With V PP < VPPL max, memory contents cannot be altered. DEVICE POWER SUPPLY: (5 V 10%) GROUND OE# INPUT WE# INPUT VPP VCC GND 7 28F001BX E 28F010 VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P28F001BX 32-Pin PDIP 0.62" x 1.64" Top View 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE# RP# A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 28F010 VCC WE# NC A14 A13 A8 A9 A11 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 0406_02 Figure 2. DIP Pin Configuration 8 E 28F001BX 29040604 Figure 3. PLCC Lead Congfiguration 9 28F001BX E 29040605 Figure 4. 28F001BX-T in a 80C188 System 29040606 Figure 5. 28F001BX-B in a 80C51 System 2.0 PRINCIPLES OF OPERATION The 28F001BX introduces on-chip write automation to manage write and erase functions. The write state machine allows for 100% TTL-level control inputs, fixed power supplies during erasure and programming, minimal processor overhead with RAM-like write timings, and maximum EPROM compatiblity. After initial device power-up, or after return from deep power-down mode (see Bus Operation), the 28F001BX functions as a read-only memory. Manipulation of external memory-control pins yield standard EPROM read, standby, output disable or intelligent identifier operations. Both status register and intelligent identifiers can be accessed through the command register when VPP = VPPL. This same subset of operations is also available when high voltage is applied to the VPP pin. In addition, high voltage on VPP enables successful erasure and programming of the device. All functions associated with altering memory contents--program, erase, status, and inteligent identifier--are accessed via the command register and verified through the status register. Commands are written using standard microprocessor write timings. Register contents serve as input to the WSM, which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for programming or erase operations. With the appropriate command written to the register, standard microprocessor read timings output array data, access the intelligent identifier codes, or output program and erase status for verification. 10 E 2.1 28F001BX Interface software to initiate and poll progress of internal program and erase can be stored in any of the 28F001BX blocks. This code is copied to, and executed from, system RAM during actual flash memory update. After successful completion of program and/or erase, code execution out of the 28F001BX is again possible via the Read Array command. Erase suspend/resume capability allows system software to suspend block erase and read data/execute code from any other block. 1FFFF 8-Kbyte Boot Block 1E000 1DFFF 1D000 1CFFF 1C000 1BFFF 4-Kbyte Parameter Block 4-Kbyte Parameter Block Command Register and Write Automation 112-Kbyte Main Block An on-chip state machine controls block erase and byte program, freeing the system processor for other tasks. After receiving the Erase Setup and Erase Confirm commands, the state machine controls block pre-conditioning and erase, returning progress via the status register. Programming is similarly controlled, after destination address and expected data are supplied. The program algorithm of past Intel Flash memories is now regulated by the state machine, including program pulse repetition where required and internal verification and margining of data. 00000 0406_06 Figure 6. 28F001BX-T Memory Map 1FFFF 2.2 Data Protection 112-Kbyte Main Block Depending on the application, the system designer may choose to make the VPP power supply switchable (available only when memory updates are required) or hardwired to VPPH. When VPP = VPPL, memory contents cannot be altered. The 28F001BX command register architecture provides protection from unwanted program or erase operations even when high voltage is applied to VPP. Additionally, all functions are disabled whenever VCC is below the write lockout voltage VLKO, or when RP# is at VIL. The 28F001BX accommodates either design practice and encourages optimization of the processor-memory interface. The two-step program/erase write sequence to the command register provides additional software write protection. 04000 03FFF 03000 02FFF 02000 01FFF 4-Kbyte Parameter Block 4-Kbyte Parameter Block 8-Kbyte Boot Block 00000 0406_07 Figure 7. 28F001BX-B Memory Map 3.0 BUS OPERATION Flash memory reads, erases and writes in-system via the local CPU. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 11 28F001BX 3.1 Read 3.2 Output Disable E The 28F001BX has three read modes. The memory can be read from any of its blocks, and information can be read from the intelligent identifier or the status register. V PP can be at either VPPL or VPPH. With OE# at a logic-high level (VIH), the device outputs are disabled. Output pins (DQ0-DQ7) are placed in a high-impedance state. The first task is to write the appropriate Read Mode 3.3 Standby command to the command register (array, intelligent identifier, or status register). The CE# at a logic-high level (VIH) places the 28F001BX 28F001BX automatically resets to read array mode in standby mode. Standby operation disables much upon initial device power-up or after exit from deep of the 28F001BX's circuitry and substantially power-down. The 28F001BX has four control pins, reduces device power consumption. The outputs two of which must be logically active to obtain data (DQ0-DQ7) are placed in a high-impedance state at the outputs. Chip Enable (CE#) is the device independent of the status of OE#. If the 28F001BX selection control, and when active enables the is deselected during erase or program, the device selected memory device. Output Enable (OE#) is will continue functioning and consuming normal the data input/output (DQ0-DQ7) direction control, active power until the operation is completed. and when active drives data from the selected memory onto the I/O bus. RP# and WE# must also be at VIH. Figure 11 illustrates read bus cycle waveforms. Table 2. 28F001BX Bus Operations Mode Read Output Disable Standby Deep Power Down Intelligent Identifier (Mfr) Notes 1, 2, 3 2 2 2 2, 3, 4 RP# VIH VIH VIH VIL VIH VIH VIH CE# VIL VIL VIH X VIL VIL VIL OE# VIL VIH X X VIL VIL VIH WE# VIH VIH X X VIH VIH VIL A9 X X X X VID VID X A0 X X X X VIL VIH X VPP X X X X X X X DQ0-7 DOUT High Z High Z High Z 89H 94H, 95H DIN Intelligent Identifier 2, 3, 4, 5 (Device) Write 2, 6, 7, 8 NOTES: 1. Refer to Section 10.4, DC Characteristics. When VPP = VPPL, memory contents can be read but not programmed or erased. 2. X can be VIL or VIH for control pins and addresses, and VPPL or VPPH for VPP. 3. See DC Characteristics, for VPPL, VPPH, VHH and VID voltages. 4. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 3. A1-A8, A10-A16 = VIL. 5. Device ID = 94H for the 28F001BX-T and 95H for the 28F001BX-B. 6. Command writes involving block erase or byte program are successfully executed only when V = VPPH. PP 7. Refer to Table 3 for valid DIN during a write operation. 8. Program or erase the boot block by holding RP# at VHH or toggling OE# to VHH. See AC waveforms for program/erase operations. 12 E 3.4 28F001BX Deep Power-Down 3.6 Write The 28F001BX offers a 0.25 W VCC power-down feature, entered when RP# is at VIL. During read modes, RP# low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. The 28F001BX requires time tPHQV (see AC Characteristics--Read-Only Operations) after return from power-down until initial memory access outputs are valid. After this wakeup interval, normal operation is restored. The command register is reset to read array, and the status register is cleared to value 80H, upon return to normal operation. During erase or program modes, RP# low will abort either operation. Memory contents of the block being altered are no longer valid as the data will be partially programmed or erased. Time tPHWL after RP# goes to logic-high (VIH) is required before another command can be written. Writes to the command register allow read of device data and intelligent identifiers. They also control inspection and clearing of the status register. Additionally, when VPP = VPPH, the command register controls device erasure and programming. The contents of the register serve as input to the internal state machine. The command register itself does not occupy an addressable memory location. The register is a latch used to store the command and address and data information needed to execute the command. Erase Setup and Erase Confirm commands require both appropriate command data and an address within the block to be erased. The Program Setup command requires both appropriate command data and the address of the location to be programmed, while the Program command consists of the data to be written and the address of the location to be programmed. The command register is written by bringing WE# to a logic-low level (VIL) while CE# is low. Addresses and data are latched on the rising edge of WE#. Standard microprocessor write timings are used. Refer to AC Characteristics--Write/Erase/Program Operations and the AC Waveform for Write Operations, Figure 19, for specific timing parameters. 3.5 Intelligent Identifier Operation The intelligent identifier operation outputs the manufacturer code, 89H; and the device code, 94H for the 28F001BX-T and 95H for the 28F001BX-B. Programming equipment or the system CPU can then automatically match the device with its proper erase and programming algorithms. 3.5.1 PROGRAMMING EQUIPMENT CE# and OE# at a logic low level (VIL), with A9 at high voltage VID (see DC Characteristics) activates this operation. Data read from locations 00000H and 00001H represent the manufacturer's code and the device code respectively. 3.5.2 IN-SYSTEM PROGRAMMING 4.0 COMMAND DEFINITIONS When VPPL is applied to the VPP pin, read operations from the status register, intelligent identifiers, or array blocks are enabled. Placing VPPH on VPP enables successful program and erase operations as well. Device operations are selected by writing specific commands into the command register. Table 3 defines these 28F001BX commands. The manufacturer and device codes can also be read via the command register. Following a write of 90H to the command register, a read from address location 00000H outputs the manufacturer code (89H). A read from address 00001H outputs the device code (94H for the 28F001BX-T and 95H for the 28F001BX-B). It is not necessary to have high voltage applied to VPP to read the intelligent identifiers from the command register. 4.1 Read Array Command Upon initial device power-up and after exit from deep power-down mode, the 28F001BX defaults to read array mode. This operation is also initiated by writing FFH into the command register. 13 28F001BX Microprocessor read cycles retrieve array data. The device remains enabled for reads until the command register contents are altered. Once the internal write state machine has started an erase or program operation, the device will not recognize the Read Array command, until the WSM has completed its operation. The Read Array command is functional when VPP = VPPL or VPPH. 4.2 Intelligent Identifier Command for In-System Programming E The 28F001BX contains an intelligent identifier operation to supplement traditional PROMprogramming methodology. The operation is initiated by writing 90H into the command register. Following the command Write, a read cycle from address 00000H retrieves the manufacturer code of 89H. A read cycle from address 00001H returns the device code of 94H (28F001BX-T) or 95H (28F001BX-B). To terminate the operation, it is necessary to write another valid command into the register. Like the Read Array command, the Intelligent Identifier command is functional when VPP = VPPL or VPPH. Table 3. 28F001BX Command Definitions First Bus Cycle Bus Cycles Req'd 1 3 2 1 2 2 2 2, 3 2 Second Bus Cycle Command Read Array/Reset Intelligent Identifier Read Status Register Clear Status Register Erase Setup/Erase Confirm Erase Suspend/ Erase Resume Program Setup/ Program Notes 1 2, 3, 4 3 Operation Write Write Write Write Write Write Write Address X X X X BA X PA Data FFH 90H 70H 50H 20H B0H 40H Operation Address Data Read Read IA X IID SRD Write Write Write BA X PA D0H D0H PD NOTES: 1. Bus operations are defined in Table 2. 2. IA = Identifier Address: 00H for manufacturer code, 01H for device code. BA = Address within the block being erased. PA = Address of memory location to be programmed. 3. SRD = Data read from status register. See Table 4 for a description of the status register bits. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE#. IID = Data read from intelligent identifiers. 4. Following the Intelligent Identifier command, two read operations access manufacture and device codes. 5. Commands other than those shown above are reserved by Intel for future device implementations and should not be used. 14 E 4.3 28F001BX Read Status Register Command 4.5 Erase Setup/Erase Confirm Commands The 28F001BX contains a status register which may be read to determine when a program or erase operation is complete, and whether that operation completed successfully. The status register may be read at any time by writing the Read Status Register command (70H) to the command register. After writing this command, all subsequent read operations output data from the status register, until another valid command is written to the command register. The contents of the status register are latched on the falling edge of OE# or CE#, whichever occurs last in the read cycle. OE# or CE# must be toggled to VIH before further reads to update the status register latch. The Read Status Register command functions when VPP = VPPL or VPPH. Erase is executed one block at a time, initiated by a two-cycle command sequence. An Erase Setup command (20H) is first written to the command register, followed by the Erase Confirm command (D0H). These commands require both appropriate command data and an address within the block to be erased. Block preconditioning, erase and verify are all handled internally by the Write State Machine, invisible to the system. After receiving the two-command erase sequence, the 28F001BX automatically outputs status register data when read (see Figure 9, 28F001BX Block Erase Flowchart). The CPU can detect the completion of the erase event by checking the WSM status bit of the status register (SR.7). When the status register indicates that erase is complete, the erase status bit should be checked. If erase error is detected, the status register should be cleared. The command register remains in read status register mode until further commands are issued to it. This two-step sequence of set-up followed by execution ensures that memory contents are not accidentally erased. Also, block erasure can only occur when VPP = VPPH. In the absence of this high voltage, memory contents are protected against erasure. If block erase is attempted while VPP = VPPL, the VPP status bit will be set to "1". Erase attempts while VPPL < VPP < VPPH produce spurious results and should not be attempted. 4.4 Clear Status Register Command The erase status and program status bits are set to "1" by the Write State Machine and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 4). By allowing system software to control the resetting of these bits, several operations may be performed (such as cumulatively programming several bytes or erasing multiple blocks in sequence). The status register may then be polled to determine if an error occurred during that series. This adds flexibility to the way the device may be used. Additionally, the VPP status bit (SR.3), when set to "1," must be reset by system software before further byte programs or block erases are attempted. To clear the status register, the Clear Status Register command (50H) is written to the command register. The Clear Status Register command is functional when VPP = VPPL or VPPH. 4.6 Erase Suspend/Erase Resume Commands The Erase Suspend command allows erase sequence interruption in order to read data from another block of memory. Once the erase sequence is started, writing the Erase Suspend command (B0H) to the command register requests that the WSM suspend the erase sequence at a predetermined point in the erase algorithm. The 28F001BX continues to output status register data when read, after the Erase Suspend command is written to it. Polling the WSM status and erase suspend status bits will determine when the erase operation has been suspended (both will be set to "1s"). 15 28F001BX At this point, a Read Array command can be written to the command register to read data from blocks other than that which is suspended. The only other valid commands at this time are Read Status Register (70H) and Erase Resume (D0H), at which time the WSM will continue with the erase sequence. The erase suspend status and WSM status bits of the status register will be cleared. After the Erase Resume command is written to it, the 28F001BX automatically outputs status register data when read (see Figure 10, 28F001BX Erase Suspend/ Resume Flowchart). E Table 4. 28F001BX Status Register Definitions WSMS 7 ESS 6 ES 5 PS 4 VPPS 3 R 2 R 1 R 0 SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy NOTES: The WSM status bit must first be checked to determine program or erase completion, before the program or erase status bits are checked for success. If the program and erase status bits are set to "1s" during an erase attempt, an improper command sequence was entered. Attempt the operation again. If VPP low status is detected, the status register must be cleared before another program or erase operation is attempted. The VPP status bit, unlike an A/D converter, does not provide continuous indication of VPP level. The WSM interrogates the VPP level only after the Program or Erase command sequences have been entered and informs the system if V PP has not been switched on. The VPP status bit is not guaranteed to report accurate feedback between VPPL and VPPH. SR.6 = ERASE SUSPEND STATUS 1 = Erase Suspended 0 = Erase in Progress/Completed SR.5 = ERASE STATUS 1 = Error in Block Erasure 0 = Successful Block Erase SR.4 = PROGRAM STATUS 1 = Error in Byte Program 0 = Successful Byte Program SR.3 = VPP STATUS 1 = VPP Low Detect; Operation Abort 0 = VPP OK SR.2-SR.0 = RESERVED FOR FUTURE ENHANCEMENTS These bits are reserved for future use and should be masked out when polling the status register. 16 E 4.7 28F001BX approximately 2 Mv/cm lower than EEPROM. The lower electric field greatly reduces oxide stress and the probability of failure. The 28F001BX-B and 28F001BX-T are capable of 100,000 program/erase cycles on each parameter block, main block and boot block. Program Setup/Program Commands Programming is executed by a two-write sequence. The Program Setup command (40H) is written to the command register, followed by a second write specifying the address and data (latched on the rising edge of WE#) to be programmed. The WSM then takes over, controlling the program and verify algorithms internally. After the two-command program sequence is written to it, the 28F001BX automatically outputs status register data when read (see Figure 8, 28F001BX Byte Programming Flowchart). The CPU can detect the completion of the program event by analyzing the WSM status bit of the status register. Only the Read Status Register command is valid while programming is active. When the status register indicates that programming is complete, the program status bit should be checked. If program error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully program to "0"s. The command register remains in read status register mode until further commands are issued to it. If byte program is attempted while VPP = VPPL, the VPP status bit will be set to "1." Program attempts while VPPL < VPP < VPPH produce spurious results and should not be attempted. 6.0 ON-CHIP PROGRAMMING ALGORITHM The 28F001BX integrates the Quick-Pulse programming algorithm of prior Intel Flash memory devices on-chip, using the command register, status register and WSM. On-chip integration dramatically simplifies system software and provides processor-like interface timings to the command and status registers. WSM operation, internal program verify and VPP high voltage presence are monitored and reported via appropriate status register bits. Figure 8 shows a system software flowchart for device programming. The entire sequence is performed with VPP at VPPH. Program abort occurs when RP# transitions to VIL, or VPP drops to VPPL. Although the WSM is halted, byte data is partially programmed at the location where programming was aborted. Block erasure or a repeat of byte programming will initialize this data to a known value. 5.0 EXTENDED ERASE/PROGRAM CYCLING EEPROM cycling failures have always concerned users. The high electrical field required by thin oxide EEPROMs for tunneling can literally tear apart the oxide at defect regions. To combat this, some suppliers have implemented redundancy schemes, reducing cycling failures to insignificant levels. However, redundancy requires that cell size be doubled; an expensive solution. Intel has designed extended cycling capability into its ETOX flash memory technology. Resulting improvements in cycling reliability come without increasing memory cell size or complexity. First, an advanced tunnel oxide increases the charge carrying ability ten-fold. Second, the oxide area per cell subjected to the tunneling electrical field is onetenth that of common EEPROMs, minimizing the probability of oxide defects in the region. Finally, the peak electric field during erasure is 7.0 ON-CHIP ERASE ALGORITHM As above, the quick-erase algorithm of prior Intel Flash memory devices is now implemented internally, including all preconditioning of block data. WSM operation, erase success and VPP high voltage presence are monitored and reported through the status register. Additionally, if a command other than Erase Confirm is written to the device after Erase Setup has been written, both the erase status and program status bits will be set to "1". When issuing the Erase Setup and Erase Confirm commands, they should be written to an address within the address range of the block to be erased. Figure 9 shows a system software flowchart for block erase. Erase typically takes 1-4 seconds per block. The Erase Suspend/Erase Resume command sequence allows interrupt of this erase operation to read datafrom a block other than that in which erase is being performed. A system software flowchart is shown in Figure 10. 17 28F001BX The entire sequence is performed with VPP at VPPH. Abort occurs when RP# transitions to VIL or VPP falls to VPPL, while erase is in progress. Block data is partially erased by this operation, and a repeat of erase is required to obtain a fully erased block. 8.1 In-System Operation E 8.0 BOOT BLOCK PROGRAM AND ERASE The boot block is intended to contain secure code which will minimally bring up a system and control programming and erase of other blocks of the device, if needed. Therefore, additional "lockout" protection is provided to guarantee data integrity. Boot block program and erase operations are enabled through high voltage VHH on either RP# or OE#, and the normal Program and Erase command sequences are used. Reference the AC waveforms for program/erase. If boot block program or erase is attempted while RP# is at VIH, either the program status or erase status bit will be set to "1", reflective of the operation being attempted and indicating boot block lock. Program/erase attempts while VIH < RP# < VHH produce spurious results and should not be attempted. For on-board programming, the RP# pin is the most convenient means of altering the boot block. Before issuing Program or Erase Confirm commands, RP# must transition to VHH. Hold RP# at this high voltage throughout the program or erase interval (until after status register confirmation of successful completion). At this time, it can return to V IH or VIL. 8.1.1 PROGRAMMING EQUIPMENT For PROM programming equipment that cannot bring RP# to high voltage, OE# provides an alternate boot block access mechanism. OE# must transition to VHH a minimum of 480 ns before the initial Program/Erase Setup command and held at VHH at least 480 ns after Program or Erase Confirm commands are issued to the device. After this interval, OE# can return to normal TTL levels. 18 E Start Bus Operation Command Program Setup Program 28F001BX Comments Data = 40H Addr = Byte to Be Programmed Data = Data to Be Programmed Addr = Byte to Be Programmed Status Register Data Toggle OE# or CE# to Update Status Register Check SR.7 1 = Ready 0 = Busy Write 40H, Byte Address Write Byte Address/Data Write Write Read Read Status Register No SR.7 = 1? Yes Full Status Check if Desired Byte Program Completed FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) No Standby Repeat for subsequent bytes. Full status check can be done after each byte, or after a sequence of bytes. Write FFH after the last byte programming operation to reset the device to read array mode. Bus Operation Standby Command Comments Check SR.3 1 = VPP Low Detect Check SR.4 1 = Byte Program Error SR.3 = 0? Yes SR.4 = 0? Yes Byte Program Successful VPP Range Error Standby No Byte Program Error SR.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. SR.4 is only cleared by the Clear Status Register command in cases where multiple locations are programmed before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. 0406_08 Figure 8. 28F001BX Byte Programming Flowchart 19 28F001BX E Start Bus Operation Write Write Command Erase Setup Erase Comments Data = 20H Addr = Within Block to Be Erased Data = D0H Addr = Within Block to Be Erased Status Register Data Toggle OE# or CE# to Update Status Register Check SR.7 1 = Ready 0 = Busy Read Standby Write 20H, Block Address Write D0H, Block Address Read Status Register No SR.7 = 1? Yes Full Status Check if Desired Block Erase Completed No Suspend Erase? Erase Suspend Loop Repeat for subsequent blocks. Yes Full status check can be done after each block, or after a sequence of blocks. Write FFH after the last block erase operation to reset the device to read array mode. FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) No SR.3 = 0? Yes Yes SR.4, 5 = 1? = No No SR.5 = 0? Yes Block Erase Successful 0406_09 Bus Operation Standby Command Comments Check SR.3 1 = VPP Low Detect Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error VPP Range Error Standby Standby Command Seq. Error SR.3 must be cleared, if set during an erase attempt, before further attempts are allowed by the write state machine. SR.5 is only cleared by the Clear Status Register command in cases where multiple blocks are erased before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. Block Erase Error Figure 9. 28F001BX Block Erase Flowchart 20 E Start Bus Operation Write Command Erase Suspend Read Status Data = B0H Addr = X Data = 70H Addr = X 28F001BX Comments Write B0H Write Write 70H Read Status Register Data Toggle OE# or CE# to Update Status Register Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.6 1 = Erase Suspended 0 = Erase Completed Read Array Data = FFH Addr = X Read array data from block other than the one being programmed Erase Resume Data = D0H Addr = X Read Status Register 0 1 SR.6 = 1 Write FFH 0 Erase Resumed Standby SR.7 = Standby Write Read Write Read Array Data Done Reading Yes Write D0H No Write FFH Erase Resumed Read Array Data 0406_10 Figure 10. 28F001BX Erase Suspend/Resume Flowchart 21 28F001BX 9.0 DESIGN CONSIDERATIONS Flash memories are often used in larger memory arrays. Intel provides three control inputs to accommodate multiple memory connections. Threeline control provides for: a) lowest possible memory power dissipation b) complete assurance that data bus contention will not occur To efficiently use these control inputs, an address decoder should enable CE#, while OE# should be connected to all memory devices and the system's READ# control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset. bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots. E 9.3 VCC, VPP, RP# Transitions and the Command/Status Registers Programming and erase completion are not guaranteed if VPP drops below VPPH. If the VPP status bit of the status register (SR.3) is set to "1", a Clear Status Register command must be issued before further program/erase attempts are allowed by the WSM. Otherwise, the program (SR.4) or erase (SR.5) status bits of the status register will be set to "1" if error is detected. RP# transitions to VIL during program and erase also abort the operations. Data is partially altered in either case, and the command sequence must be repeated after normal operation is restored. Device power-off, or RP# transitions to VIL, clear the status register to initial value 80H. The command register latches commands as issued by system software and is not altered by VPP or CE# transitions or WSM actions. Its state upon power-up, after exit from deep power-down or after VCC transitions below VLKO, is FFH, or read array mode. After program or erase is complete, even after VPP transitions down to VPPL, the command register must be reset to read array mode via the Read Array command if access to the memory array is desired. 9.1 Power Supply Decoupling Flash memory power switching characteristics require careful device coupling. System designers are interested in three supply current issues; standby current levels (ISB), active current levels (ICC) and transient peaks producted by falling and rising edges of CE#. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between its VCC and GND, and between its VPP and GND. These high frequency, low inherent-inductance capacitors should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 F electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances. 9.4 Power-Up/Down Protection The 28F001BX is designed to offer protection against accidental erasure or programming during power transitions. Upon power-up, the 28F001BX is indifferent as to which power supply, VPP or VCC, powers up first. Power supply sequencing is not required. Internal circuitry in the 28F001BX ensures that the command register is reset to read array mode on power-up. A system designer must guard against spurious writes for VCC voltages above VLKO when VPP is active. Since both WE# and CE# must be low for a command write, driving either to VIH will inhibit writes. The command register architecture provides an added level of protection since alteration of memory contents only occurs after successful completion of the two-step command sequences. 9.2 VPP Trace on Printed Circuit Boards Programming flash memories, while they reside in the target system, requires that the printed circuit board designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for programming. Use similar trace widths and layout considerations given to the VCC power 22 E 9.5 28F001BX In addition, the 28F001BX's deep power-down mode ensures extremely low power dissipation even when system power is applied. For example, laptop and other PC applications, after copying BIOS to DRAM, can lower RP# to VIL, producing negligible power consumption. If access to the boot code is again needed, as in case of a system RESET#, the part can again be accessed, following the tPHAV wakeup cycle required after RP# is first raised back to VIH. The first address presented to the device while in power-down requires time tPHAV, after RP# transitions high, before outputs are valid. Further accesses follow normal timing. See AC Characteristics--Read-Only Operations and Figure 11 for more information. Finally, the device is disabled, until RP# is brought to VIH, regardless of the state of its control inputs. This provides an additional level of protection. 28F001BX Power Dissipation When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash nonvolatility increases usable battery life because the 28F001BX does not consume any power to retain code or data when the system is off. 23 28F001BX 10.0 ELECTRICAL SPECIFICATIONS 10.1 Absolute Maximum Ratings* E NOTICE: This is a production datasheet. specifications are subject to change without notice. The Operating Temperature During Read................................. 0 C to 70 C(1) During Erase/Program.................. 0 C to 70 C(1) Operating Temperature During Read ........................... -40 C to +85 C(2) During Erase/Program............ -40 C to +85 C(2) Temperature under Bias............. -10 C to 80 C (1) Temperature under Bias........... -20 C to +90 C (2) Storage Temperature ....................-65 C to 125 C Voltage on Any Pin (except A9, RP#, OE#, V CC and VPP) with Respect to GND................. -2.0 V to 7.0 V(3) Voltage on A9, RP#, and OE# with Respect to GND.............-2.0 V to 13.5 V(3, 4) VPP Program Voltage with Respect to GND During Erase/Program...........-2.0 V to 14.0 V(3, 4) VCC Supply Voltage with Respect to GND................. -2.0 V to 7.0 V(3) Output Short Circuit Current .....................100 mA(5) *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. NOTES: 1. Operating temperature is for commercial product defined by this specification. 2. Operating temperature is for extended temperature product defined by this specification. 3. Minimum DC voltage is -0.5 V on input/output pins. During transitions, this level may undershoot to -2.0 V for periods <20 ns. Maximum DC voltage on input/output pins is VCC +0.5 V which, during transitions, may overshoot to VCC + 2.0 V for periods <20 ns. 4. Maximum DC voltage on A9 or VPP may overshoot to +14.0 V for periods <20 ns. 5. Output shorted for no more than one second. No more than one output shorted at a time. 10.2 Operating Conditions Parameter Operating Operating Temperature(1) Temperature(2) Min 0 -40 4.50 Max 70 85 5.50 Unit C C V Symbol TA TA VCC Supply Voltage 10.3 Capacitance(1) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Max 8 12 Unit pF pF Conditions VIN = 0 V VOUT = 0 V TA = 25 C, F = 1 MHz NOTE: 1. Sampled, not 100% tested. 24 E 10.4 Symbol IIL ILO ICCS ICCD ICCR 28F001BX DC Characteristics Parameter Notes 1 1 1.2 30 Min Typ Max 1.0 10 2.0 100 Unit A A mA A Test Conditions VCC = VCC Max VIN = VCC or GND VCC = VCC Max VOUT = VCC or GND VCC = VCC Max CE# = RP# = VIH VCC = VCC Max CE# = RP# = VCC 0.2 V RP# = GND 0.2 V VCC = VCC Max, CE# = VIL f = 8 MHz, I OUT = 0 mA Programming in Progress Erase in Progress Erase Suspended CE# = VIH VPP VCC VPP > VCC RP# = GND 0.2 V VPP = VPPH Programming in Progress VPP = VPPH Erase in Progress VPP = VPPH Erase Suspended A9 = VID VCC = 5.0 V 10%, TA = 0 C to +70 C Input Load Current Output Leakage Current VCC Standby Current VCC Deep Power-Down Current VCC Read Current 1 1 1.0 13 4.0 30 A mA ICCP ICCE ICCES IPPS VCC Programming Current VCC Erase Current VCC Erase Suspend Current VPP Standby Current 1 1 1, 2 1 5 6 5 1 90 20 20 10 10 200 1.0 30 mA mA mA A A A mA IPPD IPPP VPP Deep Power-Down Current VPP Programming Current 1 1 0.80 6 IPPE IPPES IID VIL VIH VOL VOH VID VPP Erase Current VPP Erase Suspend Current A9 Intelligent Identifier Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage A9 Intelligent Identifier Voltage 1 1 1 -0.5 2.0 6 90 90 30 300 500 0.8 VCC + 0.5 0.45 mA A A V V V V VCC = VCC Min IOL = 5.8 mA VCC = VCC Min IOH = 2.5 mA 2.4 11.5 13.0 V 25 28F001BX 10.4 Symbol VPPL VPPH VLKO VHH DC Characteristics (Continued) Parameter VPP during Normal Operations VPP during Prog/Erase Operations VCC Erase/Write Lock Voltage RP#, OE# Unlock Voltage Notes 3 Min 0.0 11.4 2.5 11.4 12.6 12.0 Typ Max 6.5 12.6 Unit V V V V E Test Conditions Boot Block Prog/Erase NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 12.0 V, TA = 25 C. These currents are valid for all product versions (packages and speeds). 2. ICCES is specified with the device deselected. If the 28F001BX is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Erase/programs are inhibited when VPP = VPPL and not guaranteed in the range between VPPH and VPPL. 10.4 Symbol IIL ILO ICCS DC Characteristics (Continued) Parameter Input Load Current Output Leakage Current VCC Standby Current Notes Min Typ 1 1 1.2 30 Max 1.0 10 2.0 150 2.0 35 20 20 10 15 400 1.0 30 Unit A A mA A A mA mA mA mA A A A A Test Conditions VCC = VCC Max VIN = VCC or GND VCC = VCC Max VOUT = VCC or GND VCC = VCC Max CE# = RP# = VIH VCC = VCC Max CE# = RP# = VCC 0.2 V RP# = GND 0.2 V VCC = VCC Max, CE# = V IL f = 8 MHz, I OUT = 0 mA Programming in Progress Erase in Progress Erase Suspended CE# = VIH VPP VCC VPP > VCC RP# = GND 0.2 V VPP = VPP Programming in Progress VCC = 5.0 V 10%, TA = -40 C to +85 C ICCD ICCR ICCP ICCE ICCES IPPS VCC Deep Power-Down Current VCC Read Current VCC Programming Current VCC Erase Current VCC Erase Suspend Current VPP Standby Current 1 1 1 1 1, 2 1 0.05 13 5 6 5 1 90 IPPD IPPP VPP Deep Power-Down Current VPP Programming Current 1 1 0.80 6 26 E 10.4 Symbol IPPE IPPES IID VIL VIH VOL VOH1 VOH2 28F001BX DC Characteristics (Continued) Parameter Notes Min Typ 1 1 1 -0.5 2.0 6 90 90 Max 30 400 500 0.8 VCC + 0.5 0.45 2.4 0.85 VCC VCC -0.4 Unit mA A A V V V V V VCC = VCC Min IOL = 5.8 mA VCC = VCC Min IOH = 2.5 mA VCC = VCC Min IOH = -2.5 A VCC = VCC Min IOH = -100 A 13.0 6.5 12.6 V V V V 12.6 V Boot Block Prog/Erase Test Conditions VPP = VPPH Erase in Progress VPP = VPPH Erase Suspended A9 = VID VPP Erase Current VPP Erase Suspend Current A9 Intelligent Identifier Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage (TTL) Output High Voltage (CMOS) VID VPPL VPPH VLKO VHH A9 Intelligent Identifier Voltage VPP during Normal Operations VPP during Prog/Erase Operations VCC Erase/Write Lock Voltage RP#, OE# Unlock Voltage 3 11.5 0.0 11.4 12.0 2.5 11.4 NOTES: 1. All currents are in RMS unless otherwise noted. Typical values at VCC = 5.0 V, VPP = 12.0 V, TA = 25 C. These currents are valid for all product versions (packages and speeds). 2. ICCES is specified with the device deselected. If the 28F001BX is read while in erase suspend mode, current draw is the sum of ICCES and ICCR. 3. Erase/programs are inhibited when VPP = VPPL and not guaranteed in the range between VPPH and VPPL. 27 28F001BX E 2.0 Input Test Points 0.8 2.0 Output 0.8 Figure 11. AC Input/Output Reference Waveform 1.3V 1N914 RL = 3.3 k 1.3V 1N914 RL = 3.3 k Out CL = 100 pF Device Under Test Out CL = 30 pF 2.4 0.45 AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 ns. Device Under Test NOTE: CL Includes Jig Capacitance NOTE: CL Includes Jig Capacitance Figure 12. Standard Test Configuration AC Testing Load Circuit Figure 13. High Speed Test Configuration AC Testing Load Circuit 28 E 10.5 Symbol tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tRC tCE tOE tLZ tHZ tOLZ tDF tOH 28F001BX AC Characteristics--Read-Only Operations(1) VCC 10% Parameter Read Cycle Time Address to Output Delay CE# to Output Delay RP# High to Output Delay OE# to Output Delay CE# to Output Low Z CE# High to Output High Z OE# to Output Low Z OE# High to Output High Z Output Hold from Addresses, CE# or OE# Change, Whichever is First 2 3 3 3 3 3 0 0 30 0 0 55 0 30 2 Notes Min 120 120 120 600 50 0 55 -120 Max Min 150 150 150 600 55 -150 Max Unit ns ns ns ns ns ns ns ns ns ns Version(2)a tACC tPWH NOTES: 1. See Figure 11, AC Input/Output Reference Waveform. 2. OE# may be delayed up to tCE-tOE after the falling edge of CE# without impact on tCE. 3. Sampled, not 100% tested. 29 28F001BX E 29040612 Figure 14. AC Waveform for Read Operations 30 E 10.6 Symbol tAVAV tPHWL tELWL tWLWH tPHHWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHQV1 tWHQV2 tWHQV3 tWHQV4 tWHGL tQVVL tQVPH tPHBR tWC tPS tCS tWP tVPS tAS tDS tDH tAH tCH 28F001BX AC Characteristics--Write/Erase/Program Operations(1, 9) Versions Parameter Write Cycle Time RP# High Recovery to WE# Going Low CE# Setup to WE# Going Low WE# Pulse Width RP# VHH Setup to WE# Going High VPP Setup to WE# Going High Address Setup to WE# Going High Data Setup to WE# Going High Data Hold from WE# High Address Hold from WE# High CE# Hold from WE# High WE# Pulse Width High Duration of Programming Operation Duration of Erase Operation (Boot) Duration of Erase Operation (Parameter) Duration of Erase Operation (Main) Write Recovery before Read 5, 6, 7 5, 6, 7 5, 6, 7 5, 6, 7 2 2 3 4 2 VCC 10%(10) Notes -120 Min 120 480 10 50 100 100 50 50 10 10 10 50 15 1.3 1.3 3.0 0 2, 6 2, 7 2 0 0 100 Max -150 Min 150 480 10 50 100 100 50 50< 10 10 10 50 15 1.3 1.3 3.0 0 0 0 100 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns s sec sec sec s ns ns ns tPHS tWPH tVPH tPHH VPP Hold from Valid SRD RP# VHH Hold from Valid SRD Boot-Block Relock Delay 31 28F001BX NOTES: 1. Read timing characteristics during erase and program operations are the same as during read-only operations. Refer to Section 10.5, AC Characteristics--Read-Only Operations. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid AIN for byte programming or block erasure. 4. Refer to Table 3 for valid DIN for byte programming or block erasure. 5. The on-chip WSM incorporates all program and erase system functions and overhead of standard Intel Flash memory, including byte program and verify (programming) and block precondition, precondition verify, erase and erase verify (erasing). 6. Program and erase durations are measured to completion (SR.7 = 1). VPP should be held at VPPH until determination of program/erase success (SR.3/4/5 = 0). 7. For boot block programming and erasure, RP# should be held at VHH until determination of program/erase success (SR.3/4/5 = 0). 8. Alternate boot block access method. 9. See Standard Test Configuration. E 10.6.1 PROM PROGRAMMER SPECIFICATIONS Versions VCC 10% Parameter OE# VHH Setup to WE# Going Low tPHH OE# VHH Hold from WE# High Notes 1, 2 1, 2 -120 Min 480 480 Max -150 Min 480 480 Max Unit ns ns Symbol tGHHWL tWHGH NOTES: 1. Sampled, not 100% tested. 2. Alternate boot block access method. 10.7 Erase and Programming Performance -120 Parameter Notes 2 2 2 2 2 2 2 2 Min Typ(1) 2.10 0.15 2.10 0.07 3.80 2.10 10.10 2.39 Max 14.9 0.52 14.6 0.26 20.9 7.34 65 8.38 Min -150 Typ(1) 2.10 0.15 2.10 0.07 3.80< 2.10 10.10 2.39 Max 14.9 0.52 14.6 0.26 20.9 7.34 65 8.38 Unit Sec Sec Sec Sec Sec Sec Sec Sec Boot Block Erase Time Boot Block Program Time Parameter Block Erase Time Parameter Block Program Time Main Block Erase Time Main Block Program Time Chip Erase Time Chip Program Time NOTES: 1. 25 C, 12.0 VPP. 2. Excludes System-Level Overhead. 32 E 28F001BX 29040619 29040621 Figure 15. 28F001BX Typical Programming Capability Figure 17. 28F001BX Typical Erase Capability 29040620 29040622 Figure 16. 28F001BX Typical Programming Time at 12 V Figure 18. 28F001BX Typical Erase Time at 12 V 33 28F001BX E 29040613 Figure 19. AC Waveform for Write Operations 34 E Figure 20. Alternate Boot Block Access Method Using OE# 28F001BX 29040615 35 28F001BX 10.8 AC Characteristics--CE#-Controlled Write Operations(1) Versions VCC 10% Parameter Write Cycle Time RP# High Recovery to CE# Going Low WE# Setup to CE# Going Low CE# Pulse Width RP# VHH Setup to CE# Going High VPP Setup to CE# Going High Address Setup to CE# Going High Data Setup to CE# Going High Data Hold from CE# High Address Hold from CE# High WE# Hold from CE# High CE# Pulse Width High Duration of Programming Operation Duration of Erase Operation (Boot) Duration of Erase Operation (Parameter) Duration of Erase Operation (Main) Write Recovery before Read tVPH tPHH VPP Hold from Valid SRD RP# VHH Hold from Valid SRD Boot-Block Relock Delay 2, 5 2, 6 2 5, 6 5, 6 5, 6 5, 6 2 2 3 4 2 Notes -120 Min 120 480 0 70 100 100 50 50 10 15 0 25 15 1.3 1.3 3.0 0 0 0 100 Max Min 150 480 0 70 100 100 50 50 10 15 0 25 15 1.3 1.3 3.0 0 0 0 E -150 Max Unit ns ns ns ns ns ns ns ns ns ns ns ns s sec sec sec s ns ns 100 ns Symbol tAVAV tPHEL tWLEL tELEH tPHHEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHQV1 tEHQV2 tEHQV3 tEHQV4 tEHGL tQVVL tQVPH tPHBR tWC tPS tWS tCP tPHS tVPS tAS tDS tDH tAH tWH tEPH 36 NOTES: 1. Chip-enable controlled writes: write operations are driven by the valid combination of CE# and WE#. In systems where CE# defines the write pulse width (within a longer WE# timing waveform), all set-up, hold and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% tested. 3. Refer to Table 3 for valid AIN for byte programming or block erasure. 4. Refer to Table 3 for valid DIN for byte programming or block erasure. 5. Program and erase durations are measured to completion (SR.7 = 1). VPP should be held at VPPH until determination of program/erase success (SR.3/4/5 = 0). 6. For boot block programming and erasure, RP# should be held at VHH until determination of program/erase success (SR.3/4/5 = 0). 7. Alternate boot block access method. E 10.8.1 Symbol tGHHEL tEHGH 28F001BX PROM PROGRAMMER SPECIFICATIONS Versions VCC 10% Parameter OE# VHH Setup to CE# Going Low OE# VHH Hold from CE# High Notes 1, 2 1, 2 -120 Min 480 480 Max Min 480 480 -150 Max Unit ns ns NOTES: 1. Sampled, not 100% tested. 2. Alternate boot block access method. 37 28F001BX E 29040616 Figure 21. Alternate AC Waveform for Write Operations 38 E Device Density 001 = 1 Mbit 28F001BX 11.0 ORDERING INFORMATION N2 8 F 0 0 1 BX - T 1 2 0 Operating Temperature Blank = Commercial Package N = 32-Lead PLCC P = 32-Pin PDIP Product line designator for all Intel(R) Flash products Access Speed (ns) T = Top Blocking B = Bottom Blocking Architecture BX = Boot Block VALID COMBINATIONS: N28F001BX-T120 P28F001BX-T120 N28F001BX-T150 P28F001BX-T150 N28F001BX-B120 P28F001BX-B120 N28F001BX-B150 P28F001BX-B150 12.0 ADDITIONAL INFORMATION (1,2) Order Number Note 3 Note 3 Note 3 Document AP-316 Using Flash Memory for In-System Reprogrammable Nonvolatile Storage AP-608 Implementing a Plug and Play BIOS Using Intel's Boot Block Flash Memory AP-623 Multi-Site Layout Planning Using Intel's Boot Block Flash Memory NOTE: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. Visit Intel's World Wide Web home page at http://www.intel.com for technical documentation and tools. 3. These documents can be located at the Intel World Wide Web support site, http://www.intel.com/support/flash/memory 39 |
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